IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.

《Ieee Computer Architecture Letters》是一本由Institute of Electrical and Electronics Engineers Inc.出版商出版的专业工程技术期刊，该刊创刊于2002年，刊期2 issues/year，该刊已被国际权威数据库SCIE收录。在中科院最新升级版分区表中，该刊分区信息为大类学科：工程技术 4区，小类学科：计算机：硬件 4区；在JCR（Journal Citation Reports）分区等级为Q3。该刊发文范围涵盖计算机：硬件等领域，旨在及时、准确、全面地报道国内外计算机：硬件工作者在该领域取得的最新研究成果、工作进展及学术动态、技术革新等，促进学术交流，鼓励学术创新。2021年影响因子为2.118，平均审稿速度>12周，或约稿。